【電磁技術(shù)在線】【EDA篇】- 2. 信號(hào)仿真

講師：Timo Baruth

00：00 內(nèi)容簡介

00：50 信號(hào)完整性 （PCB布局前）

02：30 CST套裝

03：45 過孔+信道 Demo （三維和電路組合）

12：50 S參數(shù)，差共模

15：30 時(shí)域 Demo （IBIS 緩沖，PRBS，眼圖）

24：00 信號(hào)完整性 （PCB布局后）

25：30 PCB導(dǎo)入+SITD 時(shí)域設(shè)置 Demo

38：15 DDR4 求解器

Signal integrity or SI is a set of measures of the quality of an electrical signal.  In digital electronics, a stream of binary values is represented by a voltage (or current) waveform.  However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise, distortion, and loss. Over short distances and at low bit rates, a simple conductor can transmit this with sufficient fidelity. At high bit rates and over longer distances or through various mediums, various effects can degrade the electrical signal to the point where errors occur and the system or device fails.

Simulation can be done in Time Domain and Frequency Domain：

Time Domain provides direct access to signal timing: Waveform/bitcharacteristics (T<rise>,T<fall>, period, overshoot, undershoot, …) Signal evolution (monotony, fly time, signal distortion at driver/receiver…)

Frequency Domain provides direct access to signal spectrum: Signal harmonics, S-parameters, Crosstalk, Impedance matching over frequency.

An IC package or PCB designer removes signal integrity problems through these techniques:

• Placing a solid reference plane adjacent to the signal traces to control crosstalk

• Controlling the trace width spacing to the reference plane to create consistent trace impedance

• Using terminations to control ringing

• Route traces perpendicular on adjacent layers to reduce crosstalk

• Increasing spacing between traces to reduce crosstalk

• Providing sufficient ground (and power) connections to limit ground bounce (this subdiscipline of signal integrity is sometimes called out separately as power integrity)

• Distributing power with solid plane layers to limit power supply noise

• Adding a preemphasis filter to the transmitter driving cell

• Adding an equalizer to the receiving cell

• Improved clock and data recovery (CDR) circuitry with low jitter/phase noise

To summarize:

• CST Studio Suite offers complete technology to conduct SI simulation.

• PCBS offers GUI to setup simulation easily.

• New DDR4 Analysis Wizard makes SI simulation of DDR4 parallel interfaces much more convenient.